H8SSLASH2218 datasheet(667/750 Pages) RENESAS

667 / 750 page

Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 619 of 698

REJ09B0074-0600

20.4

Software Standby Mode

20.4.1

Transition to Software Standby Mode

A transition is made to software standby mode when the SLEEP instruction is executed when the

SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the PSS bit in TCSR_1 are

cleared to 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However,

the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting

modules other than the A/D converter, and the states of I/O ports, are retained. In this mode the

oscillator stops, and therefore power dissipation is significantly reduced.

20.4.2

Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin,

IRQ7 pin, or IRQ0 to IRQ4

pins), RTC interrupt (

IRQ5 signal), or USB suspend/resume interrupt (IRQ6 signal), or by means

of the

RES pin, MRES pin*, or STBY pin.

• Clearing with an interrupt

When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to

the entire chip, software standby mode is cleared, and interrupt exception handling is started.

When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5

is generated. Software standby mode cannot be cleared if the interrupt has been masked on the

CPU side.

• Clearing with the RES or MRES* pin

When the

RES or MRES* pin is driven low, clock oscillation is started. At the same time as

clock oscillation starts, clocks are supplied to the entire chip. Note that the

RES or MRES* pin

must be held low until clock oscillation stabilizes. When the

RES or MRES* pin goes high, the

CPU begins reset exception handling.

• Clearing with the STBY pin

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Note: *

Supported only by the H8S/2218 Group.

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