H8SSLASH2218 datasheet(173/750 Pages) RENESAS

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Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 125 of 698

REJ09B0074-0600

6.3.5

Bus Control Register L (BCRL)

BCRL performs selection of the external bus-released state protocol, and enabling or disabling of

WAIT pin input.

The functions selected by this register are available only in the H8S/2218 Group. This register

should not be modified in the H8S/2212 Group.

Bit

Bit Name

Initial Value R/W

Description

BRLE*

R/W

Bus Release Enable

Enables or disables external bus release.

0: External bus release is disabled.

BREQ and BACK

can be used as I/O ports.

1: External bus release is enabled.

–

R/W

Reserved

The write value should always be 0.

–

Reserved

This bit is always read as 0 and cannot be modified.

–

R/W

Reserved

The write value should always be 0.

–

R/W

Reserved

The write value should always be 1.

2, 1 –

All 0

R/W

Reserved

The write value should always be 0.

WAITE*

R/W

WAIT Pin Enable

Selects enabling or disabling of wait input by the

WAIT

pin.

0: Wait input by

WAIT pin disabled. WAIT pin can be

used as I/O port.

1: Wait input by

WAIT pin enabled.

Note: * These bits should be set to 0 in the H8S/2212 Group.

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