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H8S/2218 数据表(PDF) 177 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 177 Page - Renesas Technology Corp |
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177 / 750 page ![]() Section 6 Bus Controller Rev.6.00 Jun. 03, 2008 Page 129 of 698 REJ09B0074-0600 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Wn1 Wn0 Bus Width Number of Access States Number of Program Wait States 0 0 ⎯ ⎯ 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 0 ⎯ ⎯ 8 2 0 1 0 0 3 0 1 1 1 0 2 1 3 6.4.3 Bus Interface for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (section 6.6, Basic Bus Interface and section 6.7, Burst ROM Interface) should be referred to for further details. Note that the ROM is always enabled and no external extended mode in the H8S/2212 Group. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled extended mode, all of area 0 is external space. In ROM-enabled extended mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In external extended mode, all of areas 1 to 6 is external space. When area 1 to 5 external space is accessed, the CS1 to CS5 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 to 5. Area 6 is only for the on-chip USB. For details, see section 14, Universal Serial Bus (USB). Area 7: Area 7 includes the on-chip RAM and internal l/O registers. In external extended mode, the space excluding the reserved area (for details, see section 3.4, Memory Map in Each Operating Mode) the on-chip RAM and internal l/O registers except on-chip RTC, is external space. The on- chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when |
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