H8SSLASH2218 datasheet(176/750 Pages) RENESAS

176 / 750 page

Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 128 of 698

REJ09B0074-0600

6.4.2

Bus Specifications

The external space bus specifications consist of three elements: bus width, number of access states,

and number of program wait states.

The bus width and number of access states for memory and internal I/O registers except for the on-

chip USB and RTC are fixed, and are not affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit

bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected

functions as a16-bit access space.

If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit

access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is

always set. 8-bit bus mode should be set for area 6 and area 7 in this LSI.

Number of Access States: Two or three access states can be selected with ASTCR.

An area for which 2-state access is selected functions as a 2-state access space, and an area for

which 3-state access is selected functions as a 3-state access space.

With the burst ROM interface, the number of access states may be determined without regard to

ASTCR.

When 2-state access space is designated, wait insertion is disabled.

Area 6 and area 7 should be set to function as a 3-state access space in this LSI.

Number of Program Wait States: When 3-state access space is designated by ASTCR, the

number of program wait states to be inserted automatically is selected with WCRH and WCRL.

From 0 to 3 program wait states can be selected.

The number of program wait states in area 6 and area 7 should be set to 0 in this LSI.

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