H8SSLASH2218 datasheet(179/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

179 / 750 page

Section 6 Bus Controller

Rev.6.00 Jun. 03, 2008 Page 131 of 698

REJ09B0074-0600

6.5

Basic Timing

The CPU is driven by a system clock (

φ), denoted by the symbol φ. The period from one rising

edge of

φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one,

two, or three states. Different methods are used to access on-chip memory, on-chip peripheral

modules, and the external address space.

6.5.1

On-Chip Memory (ROM, RAM) Access Timing

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 6.4 shows the on-chip memory access cycle. Figure 6.5 shows the

pin states.

Internal address bus

Bus cycle

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

access

Write

access

Figure 6.4 On-Chip Memory Access Cycle

H8S/2218 数据表(PDF) 179 Page - Renesas Technology Corp