 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H8S/2218 数据表(PDF) 239 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8S/2218 数据表(HTML) 239 Page - Renesas Technology Corp |
|
|
239 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 191 of 698 REJ09B0074-0600 Figure 7.11 illustrates operation in block transfer mode when MARA is designated as a block area. Address T B Address B B Transfer Address T A Notes: Address T A = LA Address T B = LB Address B A = LA + SAIDE · (–1) SAID · (2DTSZ · (N–1)) Address B B = LB + DAIDE · (–1) DAID · (2DTSZ · (M · N–1)) LA = Value set in MARA LB = Value set in MARB N = Value set in ETCRB M = Value set in ETCRAH and ETCRAL Address B A 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
