H8SSLASH2218 datasheet(243/750 Pages) RENESAS

243 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 195 of 698

REJ09B0074-0600

request is sent to the CPU. In case of overlap with a CPU interrupt source (DTA = 0), the interrupt

request flag is not cleared by the DMAC.

Activation by USB Request: The USB request (

DREQ signal) is specified as a DMAC activation

source. The USB request is generated by the level sense. In full-address normal mode, the USB

request is carried out as follows.

While the

DREQ signal is kept high, the DMAC waits for the transfer request. While the DREQ

signal is kept low, the DMAC releases the bus each time a byte is transferred and the transfer is

performed continuously. When the

DREQ signal is driven high during the transfer, the transfer is

halted and the DMAC waits for the transfer request.

Activation by Auto-Request: Auto-request activation is performed by register setting only, and

transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be

selected.

In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is

transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession

of the bus until the end of the transfer, and transfer is performed continuously.

H8S/2218 数据表(PDF) 243 Page - Renesas Technology Corp