H8SSLASH2218 datasheet(244/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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244 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 196 of 698

REJ09B0074-0600

7.4.8

Basic DMAC Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.14. In this example, word-

size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the

bus is transferred from the CPU to the DMAC, a source address read and destination address write

are performed. The bus is not released in response to another bus request, etc., between these read

and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.

DMAC cycle (1-word transfer)

CPU cycle

Source

address

Destination address

Address bus

HWR

LWR

Figure 7.14 Example of DMA Transfer Bus Timing

The address is not output to the external address bus in an access to on-chip memory or an internal

I/O register.

H8S/2218 数据表(PDF) 244 Page - Renesas Technology Corp