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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 248 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 248 Page - Renesas Technology Corp |
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248 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 200 of 698 REJ09B0074-0600 Full Address Mode (Block Transfer Mode): Figure 7.18 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. φ DMA read RD HWR TEND* LWR DMA write DMA dead Address bus Bus release Bus release Bus release Last block transfer DMA read Block transfer DMA write DMA read DMA write DMA dead DMA read DMA write Note: * This LSI does not support TEND output. Figure 7.18 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one- state DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. Note: * This LSI does not support TEND output. |
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