H8SSLASH2218 datasheet(246/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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246 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 198 of 698

REJ09B0074-0600

Full Address Mode (Cycle Steal Mode): Figure 7.16 shows a transfer example in which

TEND*

output is enabled and word-size full address mode transfer (cycle steal mode) is performed from

external 16-bit, 2-state access space to external 16-bit, 2-state access space.

DMA read

HWR

TEND*

LWR

DMA write

DMA read DMA write

DMA

dead

Address bus

Bus release

Last transfer cycle

Note: * This LSI does not support

TEND output.

Figure 7.16 Example of Full Address Mode (Cycle Steal) Transfer

A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the

bus is released one bus cycle is inserted by the CPU.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

Note: * This LSI does not support

TEND output.

H8S/2218 数据表(PDF) 246 Page - Renesas Technology Corp