H8SSLASH2218 datasheet(240/750 Pages) RENESAS

部件名	H8S/2218

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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240 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 192 of 698

REJ09B0074-0600

ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit

is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to

the CPU. Figure 7.12 shows the operation flow in block transfer mode.

Start

(DTE = DTME = 1)

MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH

Yes

Clear DTE bit to 0

to end transfer

Acquire bus

ETCRAL = ETCRAL–1

Transfer request?

ETCRAL = H'00

Release bus

BLKDIR = 0

ETCRAL = ETCRAH

ETCRB = ETCRB – 1

ETCRB = H'0000

Read address specified by MARA

MARA = MARA + SAIDE · (–1)SAID · 2DTSZ

Write to address specified by MARB

MARB = MARB + DAIDE · (–1)DAID · 2DTSZ

MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH

Figure 7.12 Operation Flow in Block Transfer Mode

H8S/2218 数据表(PDF) 240 Page - Renesas Technology Corp