H8SSLASH2225 datasheet(328/1071 Pages) RENESAS

部件名	H8S/2225

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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328 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 242 of 982

REJ09B0054-0500

restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR

restoration operation is as shown below.

MAR = MAR – (–1)DTID · 2DTSZ · ETCRH

The same value should be set in ETCRH and ETCRL.

In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the

transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is

not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the

operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

Figure 8.7 illustrates operation in repeat mode.

Address T

Address B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address

T = L

Address

B = L + ( 1)DTID (2DTSZ (N

1))

Where :

L = Value set in MAR

N = Value set in ETCR

Figure 8.7 Operation in Repeat mode

H8S/2225 数据表(PDF) 328 Page - Renesas Technology Corp