H8SSLASH2225 datasheet(71/1071 Pages) RENESAS

71 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxxi of lxxxvi

Figure 11.34 Input Capture Input Signal Timing......................................................................... 428

Figure 11.35 Counter Clear Timing (Compare Match) ............................................................... 428

Figure 11.36 Counter Clear Timing (Input Capture) ................................................................... 429

Figure 11.37 Buffer Operation Timing (Compare Match)........................................................... 429

Figure 11.38 Buffer Operation Timing (Input Capture) .............................................................. 430

Figure 11.39 TGI Interrupt Timing (Compare Match) ................................................................ 430

Figure 11.40 TGI Interrupt Timing (Input Capture) .................................................................... 431

Figure 11.41 TCIV Interrupt Setting Timing............................................................................... 431

Figure 11.42 TCIU Interrupt Setting Timing............................................................................... 432

Figure 11.43 Timing for Status Flag Clearing by CPU ............................................................... 432

Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation ................................ 433

Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 434

Figure 11.46 Contention between TCNT Write and Clear Operations........................................ 435

Figure 11.47 Contention between TCNT Write and Increment Operations ................................ 435

Figure 11.48 Contention between TGR Write and Compare Match............................................ 436

Figure 11.49 Contention between Buffer Register Write and Compare Match........................... 437

Figure 11.50 Contention between TGR Read and Input Capture ................................................ 437

Figure 11.51 Contention between TGR Write and Input Capture ............................................... 438

Figure 11.52 Contention between Buffer Register Write and Input Capture............................... 439

Figure 11.53 Contention between Overflow and Counter Clearing............................................. 439

Figure 11.54 Contention between TCNT Write and Overflow.................................................... 440

Section 12 8-Bit Timers

Figure 12.1 Block Diagram of 8-Bit Timer Module.................................................................. 442

Figure 12.2 Example of Pulse Output........................................................................................ 453

Figure 12.3 Count Timing for Internal Clock Input................................................................... 453

Figure 12.4 Count Timing for External Clock Input ................................................................. 454

Figure 12.5 Timing of CMF Setting .......................................................................................... 454

Figure 12.6 Timing of Timer Output ......................................................................................... 455

Figure 12.7 Timing of Compare-Match Clear ........................................................................... 455

Figure 12.8 Timing of Clearing by External Reset Input........................................................... 456

Figure 12.9 Timing of OVF Setting........................................................................................... 456

Figure 12.10 Contention between TCNT Write and Clear .......................................................... 459

Figure 12.11 Contention between TCNT Write and Increment................................................... 460

Figure 12.12 Contention between TCOR Write and Compare-Match......................................... 460

Section 13 Watchdog Timer (WDT)

Figure 13.1 Block Diagram of WDT_0 (1) ............................................................................... 466

Figure 13.1 Block Diagram of WDT_1 (2) ............................................................................... 467

Figure 13.2 Watchdog Timer Mode Operation.......................................................................... 474

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