H8SSLASH2225 datasheet(75/1071 Pages) RENESAS

75 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxxv of lxxxvi

Figure 17.2 Access to ADDR (When Reading H'AA40)........................................................... 696

Figure 17.3 Example of A/D converter Operation (Single Mode, Channel 1 Selected) ............ 698

Figure 17.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to

AN2 Selected) ........................................................................................................ 699

Figure 17.5 A/D Conversion Timing......................................................................................... 700

Figure 17.6 External Trigger Input Timing ............................................................................... 701

Figure 17.7 A/D Conversion Accuracy Definitions................................................................... 703

Figure 17.8 A/D Conversion Accuracy Definitions................................................................... 703

Figure 17.9 Example of Analog Input Circuit ........................................................................... 704

Figure 17.10 Example of Analog Input Protection Circuit .......................................................... 706

Figure 17.11 Analog Input Pin Equivalent Circuit ...................................................................... 706

Section 18 D/A Converter

Figure 18.1 Block Diagram of D/A Converter .......................................................................... 707

Figure 18.2 D/A Converter Operation Example ........................................................................ 710

Section 20 Flash Memory (F-ZTAT Version)

Figure 20.1 Block Diagram of Flash Memory........................................................................... 716

Figure 20.2 Flash Memory State Transitions............................................................................. 717

Figure 20.3 Boot Mode (Example) ............................................................................................ 718

Figure 20.4 User Program Mode (Example).............................................................................. 719

Figure 20.5 Block Configuration of 384-kbyte Flash Memory ................................................. 721

Figure 20.6 Block Configuration of 256-kbyte Flash Memory ................................................. 722

Figure 20.7 Block Configuration of 128-kbyte Flash Memory ................................................. 723

Figure 20.8 Programming/Erasing Flowchart Example in User Program Mode ....................... 735

Figure 20.9 Flowchart for Flash Memory Emulation in RAM .................................................. 736

Figure 20.10 Example of RAM Overlap Operation..................................................................... 737

Figure 20.11 Program/Program-Verify Flowchart....................................................................... 739

Figure 20.12 Erase/Erase-Verify Flowchart ................................................................................ 741

Figure 20.13 Socket Adapter Pin Correspondence Diagram ....................................................... 744

Figure 20.14 Power-On/Off Timing (Boot Mode) ...................................................................... 748

Figure 20.15 Power-On/Off Timing (User Program Mode) ........................................................ 749

Figure 20.16 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program

Mode) ..................................................................................................................... 750

Section 21 Masked ROM

Figure 21.1 Block Diagram of On-Chip Masked ROM (384 kbytes)....................................... 754

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