H8SSLASH2225 datasheet(22/1071 Pages) RENESAS

22 / 1071 page

Rev. 5.00 Aug 08, 2006 page xxii of lxxxvi

Item

Page

Revision (See Manual for Details)

368

Table 11.3 amended

Channel 0, 3*

11.3.1 Timer Control

Table 11.3 CCLR2 to

CCLR0 (Channels 0 and 3)

Note 3 added

Note: 3. Not available in the H8S/2227 Group.

368

Table 11.4 amended

Channel 1, 2, 4*

3, 5*3

Table 11.4 CCLR2 to

CCLR0 (Channels 1, 2, 4,

and 5)

Note 3 added

Note: 3. Not available in the H8S/2227 Group.

11.3.2 Timer Mode Register

(TMDR)

372

Description amended

... for each channel. The TPU of the H8S/2227 Group has a

total of three TMDR registers, one each for channels 0 to 2.

In other groups, the TPU has a total of six TMDR registers,

one each for channels 0 to 5. TMDR register settings ...

BFB and BFA description amended

... In channels 1, 2, 4*, and 5*, which have no ...

Note * added

Note: * Not available in the H8S/2227 Group.

11.3.3 Timer I/C Control

373

Description amended

... the TGR registers. The TPU of the H8S/2227 Group has a

total of four TIOR registers, two for channel 0 and one each

for channels 1 and 2. In other groups, the TPU has a total of

eight TIOR registers, two each for channels 0 and 3, and

one each for channels 1, 2, 4, and 5. Care is required since

...

374

TIORH_0, TIOR_1, TIOR_2, TIORH_3*, TIOR_4*, TIOR_5*

Note * added

Note: * Not available in the H8S/2227 Group.

TIORL_0, TIORL_3*

Note * added

Note: * Not available in the H8S/2227 Group.

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