H8SSLASH2225 datasheet(42/1071 Pages) RENESAS

42 / 1071 page

Rev. 5.00 Aug 08, 2006 page xlii of lxxxvi

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24.1.2 Module Stop Control

Registers A to C (MSTPCRA

to MSTPCRC)

789

• MSTPCRA

Target module description of MSTPA0 amended

8-bit timer (TMR_2*

3, TMR_3*3)

• MSTPCRB

Target module description of MSTPB5 amended

Serial communication interface 2 (SCI_2*

790

• MSTPCRC

Bit 3 description amended

(Before) MSTPC3*

*5 → (After) MSTPC3

(Before) IEBus controller

→ (After) IEBus controller*

Notes 3 and 4 amended

Notes: 3. Not available in the H8S/2237 Group and

H8S/2227 Group.

4. Not available in the H8S/2227 Group.

790

Description amended

... The bus masters other than the CPU (DMAC* and DTC)...

24.2 Medium-Speed Mode 791

Notes * added

Note: * Supported only by the H8S/2239 Group.

24.4.3 Oscillation Settling

Time after Clearing Software

Standby Mode

Table 24.3 Oscillation

Settling Time Settings

793

Table 24.3 amended

STS2 STS1 STS0 Standby Time

MHz*

Unit

8192 states

1.4

2.0

4.1

16384 states

2.7

4.1

8.2

32768 states

5.5

8.2

16.4

65536 states

10.9

16.4

32.8

131072 states

21.8

32.8

65.5

262144 states

43.7

65.5

131.1

Reserved





16 states

2.7

4.0

8.0

µs

Notes 1 and 2 amended

Notes: 1. Supported only by the H8S/2239 Group.

2. The H8S/2258 Group is out of operation.

24.6 Module Stop Mode

796

Note * added

DMAC*

Note: * Supported only by the H8S/2239 Group only.

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