H8SSLASH2225 datasheet(80/1071 Pages) RENESAS

80 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxxx of lxxxvi

Table 9.7

Number of States Required for Each Execution Status .......................................... 301

Section 10 I/O Ports

Table 10.1

Port Functions ........................................................................................................ 306

Table 10.2

Input Pull-Up MOS States in Port A ...................................................................... 332

Table 10.3

Input Pull-Up MOS States in Port B ...................................................................... 339

Table 10.4

Input Pull-Up MOS States in Port C ...................................................................... 342

Table 10.5

Input Pull-Up MOS States in Port D ...................................................................... 346

Table 10.6

Input Pull-Up MOS States in Port E ...................................................................... 349

Section 11 16-Bit Timer Pulse Unit (TPU)

Table 11.1

TPU Functions........................................................................................................ 360

Table 11.2

Pin Configuration ................................................................................................... 364

Table 11.3

CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 368

Table 11.4

CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 368

Table 11.5

TPSC2 to TPSC0 (Channel 0)................................................................................ 369

Table 11.6

TPSC2 to TPSC0 (Channel 1)................................................................................ 369

Table 11.7

TPSC2 to TPSC0 (Channel 2)................................................................................ 370

Table 11.8

TPSC2 to TPSC0 (Channel 3)................................................................................ 370

Table 11.9

TPSC2 to TPSC0 (Channel 4)................................................................................ 371

Table 11.10 TPSC2 to TPSC0 (Channel 5)................................................................................ 371

Table 11.11 MD3 to MD0.......................................................................................................... 373

Table 11.12 TIORH_0 .............................................................................................................. 375

Table 11.13 TIORL_0 .............................................................................................................. 376

Table 11.14 TIOR_1

.............................................................................................................. 377

Table 11.15 TIOR_2

.............................................................................................................. 378

Table 11.16 TIORH_3 .............................................................................................................. 379

Table 11.17 TIORL_3 .............................................................................................................. 380

Table 11.18 TIOR_4

.............................................................................................................. 381

Table 11.19 TIOR_5

.............................................................................................................. 382

Table 11.20 TIORH_0 .............................................................................................................. 383

Table 11.21 TIORL_0 .............................................................................................................. 384

Table 11.22 TIOR_1

.............................................................................................................. 385

Table 11.23 TIOR_2

.............................................................................................................. 386

Table 11.24 TIORH_3 .............................................................................................................. 387

Table 11.25 TIORL_3 .............................................................................................................. 388

Table 11.26 TIOR_4

.............................................................................................................. 389

Table 11.27 TIOR_5

.............................................................................................................. 390

Table 11.28 Register Combinations in Buffer Operation........................................................... 405

Table 11.29 Cascaded Combinations ......................................................................................... 409

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