H8SSLASH2225 datasheet(34/1071 Pages) RENESAS

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Rev. 5.00 Aug 08, 2006 page xxxiv of lxxxvi

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15.4 Operation in

Asynchronous Mode

585

Description amended

... when the ABCS bit in SEMR_0 is 1 (H8S/2239 Group

only).

587

Description amended

... N : Bit rate ratio relative to clock (N = 16, but in the

H8S/2239 Group N = 8 if ABCS in SEMR_0 is set to 1.)

15.4.2 Receive Data

Sampling Timing and

Reception Margin in

Asynchronous Mode

Note amended

Note: Example for H8S/2239 Group with the ABCS bit in

SEMR_0 set to a value other than 1. When ABCS is ...

Figure 15.6 Receive Data

Sampling Timing in

Asynchronous Mode

588

Note amended

Note: Example for H8S/2239 Group with the ABCS bit in

SEMR_0 set to a value other than 1. When ABCS is ...

589

Figure 15.8 amended

Set TE and RE*

1 bits in SCR to 1, ...

[3] ... bits ACS2 to ACS0 in SEMR_0*

2 is used.

15.4.4 SCI Initialization

(Asynchronous Mode)

Figure 15.8 Sample SCI

Initialization Flowchart

Note 2 added

Note: 2. Supported only by the H8S/2239 Group.

15.5.2 Multiprocessor Serial

Data Reception

Figure 15.16 Sample

Multiprocessor Serial

Reception Flowchart (1)

600

Figure 15.16 amended

(Before) Read MPIE bit in SCR

→ (After) Set MPIE bit in

SCR to 1

15.10.5 Restrictions on Use

of DMAC* or DTC

Figure 15.38 Example of

Clocked Synchronous

Transmission by DMAC* or

DTC

626

Note * added

Note: * Supported only by the H8S/2239 Group.

16.1 Features

633

Description amended

• Selection of I

2C bus format or clocked synchronous

serial format

634

Description amended

•

Interrupt sources

Data transfer end ...

Address match: when ... in slave receive mode

Start condition detection (in master mode)

Stop condition detection (in slave mode)

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