H8SSLASH2225 datasheet(36/1071 Pages) RENESAS

36 / 1071 page

Rev. 5.00 Aug 08, 2006 page xxxvi of lxxxvi

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16.4.4 Master Receive

Operation

662

Description amended

[6] Clear the IRIC flag to 0. The reading of the ICDR flag

described in step [5] and the clearing of the IRIC flag to 0

should be performed consecutively, with no interrupt

processing occurring between them. During wait operation,

clear the IRIC flag to 0 when the value of counter BC2 to

BC0 is 2 or greater. If the IRIC flag is cleared to 0 when the

value of counter BC2 to BC0 is 1 or 0, it will not be possible

to determine when the transfer has completed. If condition

[3]-1 is true, ...

[11] Clear the IRIC flag to 0. As in step [6], read the ICDR

flag and clear the IRIC flag to 0 consecutively, with no

interrupt processing occurring between them. During wait

operation, clear the IRIC flag to 0 when the value of counter

BC2 to BC0 is 2 or greater.

Figure 16.13 Example of

Master Receive Mode top

condition Generation Timing

(MLS = ACKB = 0, WAIT = 1)

664

Figure 16.13 amended

Data 2

Data 3

Data 2

Data 1

[3]

[8]

[12]

Stop condition

generated

[4] IRTR = 0

Bit 6

Bit 5

Bit 4 Bit 3

Bit 2

Bit 1 Bit 0

Bit 0

1 clock cycle wait time

Bit 7

[4] IRTR = 1

[13] IRTR = 1

[13] IRTR = 0

[15] WAIT cleared to 0

IRIC clearance

[14] IRIC clearance

[11] IRIC clearance

[6] IRIC clearance

User processing

[10] ICDR read (data 2)

[16] ICDR read (data 3)

[9] TRS set to 1

[7] ACKB set to 1

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

[17] Stop condition

issued

16.4.5 Slave Receive

Operation

666

Description amended

(5) Read ICDR and clear the IRIC flag in ICCR to 0. The

RDRF flag is cleared to 0. Read the IRDR flag and clear the

IRIC flag to 0 consecutively, with no interrupt processing

occurring between them. If the time needed to transmit one

byte of data elapses before the IRIC flag is cleared, it will not

be possible to determine when the transfer has completed.

Figure 16.15 Example of

Slave Receive Mode

Operation Timing (1) (MLS =

ACKB = 0)

667

Description of "Interrupt request generation" deleted from

figure 16.15

Figure 16.16 Example of

Slave Receive Mode

Operation Timing (2) (MLS =

ACKB = 0)

668

Description of "Interrupt request generation" deleted from

figure 16.16

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