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H8S/2225 数据表(PDF) 12 Page - Renesas Technology Corp

部件名 H8S/2225
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2225 数据表(HTML) 12 Page - Renesas Technology Corp

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Rev. 5.00 Aug 08, 2006 page xii of lxxxvi
Item
Page
Revision (See Manual for Details)
5.3.4 IRQ Status Register
(ISR)
134
Description amended
ISR indicates the status of IRQn (n=7 to 0) interrupt
requests.
6.3.4 Operation in Transition
to Power-Down Modes
161,
162
Description amended
• When the SLEEP instruction causes a transition from
high-speed (medium-speed) mode to sleep mode, or
from subactive mode to subsleep mode: After execution
of the SLEEP instruction, a transition is not made to
sleep mode or subsleep mode, and PC break interrupt
handling is executed. ...
• When the SLEEP instruction causes a transition to
software standby mode or watch mode:
8.3 Register Descriptions
205
Description amended
• Transfer count register_0A (ETCR_0A)
• Transfer count register_0B (ETCR_0B)
8.7.1 DMAC Register
Access during Operation
Figure 8.38 DMAC
Register Update Timing
276
Figure 8.38 amended
DMA read
DMA write
DMA
dead
DMA last transfer cycle
Transfer
destination
nsfer
urce
Idle
ead
Dead
Write
[2']
[3]
9.1 Features
Figure 9.1 Block Diagram of
DTC
282
Figure 9.1 amended
(Before) DTCERA to DTCERF, DTCERI
→ (After) DTCERA
to DTCERG, DTCERI
9.2 Register Descriptions
283
Description amended
... When activated, ... back to the RAM.
• DTC Enable Registers A to G, and I (DCTERA to
DTCERG, and DTCERI) ...



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