H8SSLASH2225 datasheet(67/1071 Pages) RENESAS

67 / 1071 page

Rev. 5.00 Aug 08, 2006 page lxvii of lxxxvi

Figure 2.9

General Register Data Formats (2)......................................................................... 77

Figure 2.10 Memory Data Formats............................................................................................ 78

Figure 2.11 Instruction Formats (Examples) ............................................................................. 90

Figure 2.12 Branch Address Specification in Memory Indirect Mode ...................................... 93

Figure 2.13 State Transitions ..................................................................................................... 97

Figure 2.14 Flowchart for Access Methods for Registers That Include Write-Only Bits.......... 101

Section 3 MCU Operating Modes

Figure 3.1

H8S/2258 Memory Map in Each Operating Mode................................................. 109

Figure 3.2

H8S/2256 Memory Map in Each Operating Mode................................................. 110

Figure 3.3

H8S/2239 Memory Map in Each Operating Mode................................................. 111

Figure 3.4

H8S/2238B and H8S/2238R Memory Map in Each Operating Mode ................... 112

Figure 3.5

H8S/2236B and H8S/2236R Memory Map in Each Operating Mode ................... 113

Figure 3.6

H8S/2237 and H8S/2227 Memory Map in Each Operating Mode......................... 114

Figure 3.7

H8S/2235 and H8S/2225 Memory Map in Each Operating Mode......................... 115

Figure 3.8

H8S/2224 Memory Map in Each Operating Mode................................................. 116

Figure 3.9

H8S/2233 and H8S/2223 Memory Map in Each Operating Mode......................... 117

Section 4 Exception Handling

Figure 4.1

Reset Sequence (Mode 4)....................................................................................... 122

Figure 4.2

Stack Status after Exception Handling (Advanced Mode) ..................................... 125

Figure 4.3

Operation When SP Value Is Odd.......................................................................... 126

Section 5 Interrupt Controller

Figure 5.1

Block Diagram of Interrupt Controller................................................................... 128

Figure 5.2

Block Diagram of IRQn Interrupts......................................................................... 135

Figure 5.3

Set Timing for IRQnF ............................................................................................ 136

Figure 5.4

Block Diagram of Interrupt Control Operation ...................................................... 143

Figure 5.5

Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0. 146

Figure 5.6

Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 ............... 148

Figure 5.7

Interrupt Exception Handling ................................................................................. 149

Figure 5.8

DTC and DMAC Interrupt Control ........................................................................ 152

Figure 5.9

Contention between Interrupt Generation and Disabling ....................................... 155

Section 6 PC Break Controller (PBC)

Figure 6.1

Block Diagram of PC Break Controller ................................................................. 158

Figure 6.2

Operation in Power-Down Mode Transitions......................................................... 162

Section 7 Bus Controller

Figure 7.1

Block Diagram of Bus Controller........................................................................... 166

H8S/2225 数据表(PDF) 67 Page - Renesas Technology Corp

H8S/2225 数据表(HTML) 67 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载