H8SSLASH2225 datasheet(333/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 247 of 982

REJ09B0054-0500

Single address

mode setting

Set DMABCRH

Set transfer source and

transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Single address mode

[1]

[2]

[3]

[4]

[5]

[6]

[1]

Set each bit in DMABCRH.

Clear the FAE bit to 0 to select short address

mode.

Set the SAE bit to 1 to select single address

mode.

Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2]

Set the transfer source address/transfer

destination address in MAR.

[3]

Set the number of transfers in ETCR.

[4]

Set each bit in DMACR.

Set the transfer data size with the DTSZ bit.

Specify whether MAR is to be incremented or

decremented with the DTID bit.

Clear the RPE bit to 0 to select sequential

mode.

Specify the transfer direction with the DTDIR

bit.

Select the activation source with bits DTF3 to

DTF0.

[5]

Read the DTE bit in DMABCRL as 0.

[6]

Set each bit in DMABCRL.

Specify enabling or disabling of transfer end

interrupts with the DTIE bit.

Set the DTE bit to 1 to enable transfer.

Figure 8.11 Example of Single Address Mode Setting Procedure

(when Sequential Mode Is Specified)

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