H8SSLASH2225 datasheet(349/1071 Pages) RENESAS

349 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 263 of 982

REJ09B0054-0500

DREQ

DREQ Pin Low Level Activation Timing (Normal Mode): Set the DTA bit in DMABCRH to 1

for the channel for which the

DREQ pin is selected.

Figure 8.25 shows an example of normal mode transfer activated by the

DREQ pin low level.

DMA

read

DMA

write

Address

bus

DREQ

Idle

Write

Idle

Bus

release

DMA

control

Channel

Write

Idle

Transfer source

Bus

release

DMA

read

DMA

write

Bus

release

Request

[1]

[3]

[2]

[4]

[6]

[5]

[7]

Acceptance resumes

Transfer destination

Transfer source

Transfer destination

Request

Request clear period

Read

Minimum

of 2 cycles

Minimum

of 2 cycles

[1]

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMA cycle is started.

[4] [7] Acceptance is resumed after the write cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 8.25 Example of

DREQ

DREQ Pin Low Level Activated Normal Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared. After the end of the write cycle, acceptance resumes,

DREQ pin low level

sampling is performed again, and this operation is repeated until the transfer ends.

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