H8SSLASH2225 datasheet(459/1071 Pages) RENESAS

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Section 11 16-Bit Timer Pulse Unit (TPU)

Rev. 5.00 Aug 08, 2006 page 373 of 982

REJ09B0054-0500

Table 11.11 MD3 to MD0

Bit 3

MD3*

Bit 2

MD2*

Bit 1

MD1

Bit 0

MD0

Description

Normal operation

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

××

—

Legend:

×: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

11.3.3

Timer I/O Control Register (TIOR)

The TIOR registers control the TGR registers. The TPU of the H8S/2227 Group has a total of four

TIOR registers, two for channel 0 and one each for channels 1 and 2. In other groups, the TPU has

a total of eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4,

and 5. Care is required since TIOR is affected by the TMDR setting.

The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is

cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is

cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

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