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H8S/2225 数据表(PDF) 521 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 521 Page - Renesas Technology Corp |
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521 / 1071 page ![]() Section 11 16-Bit Timer Pulse Unit (TPU) Rev. 5.00 Aug 08, 2006 page 435 of 982 REJ09B0054-0500 Counter clearing signal Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N H'0000 Figure 11.46 Contention between TCNT Write and Clear Operations 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT input clock Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 11.47 Contention between TCNT Write and Increment Operations |
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