H8SSLASH2225 datasheet(861/1071 Pages) RENESAS

861 / 1071 page

Section 23 Clock Pulse Generator

Rev. 5.00 Aug 08, 2006 page 775 of 982

REJ09B0054-0500

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (1)

(H8S/2258 Group)

VCC = 4.0 V to 5.5 V

Item

Symbol

Min

Max

Unit

Test Conditions

External clock input low

pulse width

tEXL

—

External clock input high

pulse width

tEXH

—

External clock rise time

tEXr

—7

External clock fall time

tEXf

—7

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

Table 23.4 External Clock Input Conditions (Duty Adjustment Circuit Unused) (2)

(H8S/2238B, H8S/2236B)

F-ZTAT

Masked ROM

VCC = 3.0 V to 5.5 V

VCC = 2.7 V to 5.5 V

Item

Symbol

Min

Max

Min

Max

Unit

Test

Conditions

External clock input

low pulse width

tEXL

—

External clock input

high pulse width

tEXH

—

External clock rise

time

tEXr

—7

—

External clock fall

time

tEXf

—7

—

Figure 23.5

Note: If the duty adjustment circuit is not used, the maximum operating frequency will be lower to

match the input waveform.

(Example: If tEXL = tEXH = 37 ns and tEXr = tEXf = 7 ns, the clock cycle = 88 ns and the

maximum operating frequency = 11.3 MHz)

H8S/2225 数据表(PDF) 861 Page - Renesas Technology Corp

H8S/2225 数据表(HTML) 861 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载