H8SSLASH2225 datasheet(983/1071 Pages) RENESAS

983 / 1071 page

Section 27 Electrical Characteristics

Rev. 5.00 Aug 08, 2006 page 897 of 982

REJ09B0054-0500

(1) Clock Timing

Table 27.30 lists the clock timing

Table 27.30 Clock Timing

Condition A (F-ZTAT version):

VCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Condition B (Masked ROM version): VCC = 2.7 V to 5.5 V, AVCC = 3.6 V to 5.5 V,

Vref = 3.6 V to AVCC, VSS = AVSS = 0 V,

φ = 32.768 kHz, 2 MHz to 13.5 MHz,

Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Conditions A, B

Item

Symbol

Min

Typ

Max

Unit

Test

Conditions

Clock cycle time

tcyc



500

Clock high pulse width

tCH



Clock low pulse width

tCL



Clock rise time

tCr



Clock fall time

tCf



Figure 27.10

Reset oscillation stabilization

time (crystal)

tOSC1



Figure 27.11

Software standby oscillation

stabilization time (crystal)

tOSC2



External clock output stabilization

delay time

tDEXT

500



µs

Figure 27.11

Subclock oscillation stabilization

time

tOSC3



Subclock oscillator frequency

fSUB



32.768



kHz

Subclock (

φSUB) cycle time

tSUB



30.5



µs

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