H8SSLASH2225 datasheet(159/1071 Pages) RENESAS

159 / 1071 page

Section 2 CPU

Rev. 5.00 Aug 08, 2006 page 73 of 982

REJ09B0054-0500

SP (ER7)

Free area

Stack area

Figure 2.8 Stack Status

2.4.2

Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an

instruction is fetched, the least significant PC bit is regarded as 0).

2.4.3

Extended Control Register (EXR)

EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.

When these instructions except for the STC instruction is executed, all interrupts including NMI

will be masked for three states after execution is completed.

Bit

Bit Name

Initial Value

R/W

Description

R/W

Trace Bit

When this bit is set to 1, a trace exception is

generated each time an instruction is

executed. When this bit is cleared to 0,

instructions are executed in sequence.

6 to 3

—

All 1

—

Reserved

These bits are always read as 1.

R/W

These bits designate the interrupt mask level

(0 to 7). For details, refer to section 5, Interrupt

Controller.

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