H8SSLASH2225 datasheet(231/1071 Pages) RENESAS

231 / 1071 page

Section 5 Interrupt Controller

Rev. 5.00 Aug 08, 2006 page 145 of 982

REJ09B0054-0500

5.5.2

Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts, IRQ interrupts and on-chip peripheral module interrupts

can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared

to 0, and disabled when set to 1.

Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held

pending. If the I bit is cleared, an interrupt request is accepted.

3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to

the priority system is accepted, and other interrupt requests are held pending.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

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