H8SSLASH2225 datasheet(267/1071 Pages) RENESAS

267 / 1071 page

Section 7 Bus Controller

Rev. 5.00 Aug 08, 2006 page 181 of 982

REJ09B0054-0500

7.5.3

External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 7.6.3, Basic Timing.

7.6

Basic Bus Interface

The basic bus interface enables direct connection of ROM, SRAM, and so on.

7.6.1

Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external space, controls whether the

upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus

specifications for the area being accessed (8-bit access space or 16-bit access space) and the data

size.

8-Bit Access Space: Figure 7.8 illustrates data alignment control for the 8-bit access space. With

the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of

data that can be accessed at one time is one byte: a word transfer instruction is performed as two-

byte accesses, and a longword transfer instruction, as four-byte accesses.

Upper data bus

Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Longword

size

• Even address

Byte size

• Odd address

D15

D8 D7

Figure 7.8 Access Sizes and Data Alignment Control (8-Bit Access Space)

16-Bit Access Space: Figure 7.9 illustrates data alignment control for the 16-bit access space.

With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are

used for accesses. The amount of data that can be accessed at one time is one byte or one word,

and a longword transfer instruction is executed as two word transfer instructions.

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