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H8S/2225 数据表(PDF) 322 Page - Renesas Technology Corp |
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H8S/2225 数据表(HTML) 322 Page - Renesas Technology Corp |
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322 / 1071 page ![]() Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 236 of 982 REJ09B0054-0500 8.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.5 summarizes register functions in sequential mode. Table 8.5 Register Functions in Sequential Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented/ decremented every transfer 23 0 IOAR 15 H'FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 0 ETCR 15 Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 8.3 illustrates operation in sequential mode. |
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