SH7708 datasheet(208/633 Pages) RENESAS

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10.1.3

Pin Configuration

Table 10.1 lists the BSC pins.

Table 10.1

Pin Configuration

Pin Name

Signal

I/O

Description

Address bus

A25–A0

Address output

Data bus

D31–D24,

D15–D0

I/O

Data I/O

When port function is used, D31–D24 cannot be

used. Leave these pins open.

Data bus/port

D23–D16/

PORT7–PORT0

I/O

When port function is not used, data I/O; when port

function is used, port (I/O is set by register for each

bit)

Bus cycle start

Shows start of bus cycle. During burst transfers,

asserts every data cycle.

Chip select 6–0

CS6–CS0

Chip select signal to indicate area being accessed.

CS5 and CS6 can also be used as CE1A and CE1B

of PCMCIA.

Read/write

RD/

Data bus direction indicator signal.

DRAM/synchronous DRAM/PCMCIA write indicator

signal.

Row address

strobe

RAS/CE

When DRAM/synchronous DRAM is used, RAS

signal. When pseudo-SRAM is used,

CE signal.

Column address

strobe

CAS/CASLL/

When synchronous DRAM is used,

CAS signal.

When DRAM is used,

CAS signal for D7–D0. When

pseudo-SRAM is used,

OE/RFSH signal.

Column address

strobe LH

CASLH

When DRAM is used,

CAS signal for D15–D8

Column address

strobe HL

CASHL, CAS2L O

When DRAM is used,

CAS signal for D23–D16.

When the area 2 DRAM is being used,

CAS signal

for D7–D0.

Column address

strobe HH

CASHH, CAS2H O

When DRAM is used,

CAS signal for D31–D24.

When the area 2 DRAM is being used,

CAS signal

for D15–D8.

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