SH7708 datasheet(211/633 Pages) RENESAS

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10.1.5

Area Overview

Space Allocation: The SH7708 Series architecture provides for a 32-bit virtual address space. The

virtual space is divided into five areas by the value of the upper bits of the address. The physical

space is divided into eight areas with a 29-bit address space.

Virtual space can be allocated at will to physical spaces using a memory management unit

(MMU). For details, refer to section 3, Memory Management Unit, which describes area

allocation for physical spaces.

As shown in table 10.4, the SH7708 Series can be connected directly to seven areas of memory/PC

card, and it outputs chip select signals (

CS0–CS6, CE2A, CE2B) for each of them. CS0 is asserted

during area 0 access;

CS6 is asserted during area 6 access. When DRAM, synchronous DRAM, or

pseudo-SRAM is connected to area 2 or 3, signals such as

RAS, CAS, RD/WR, and DQM are also

asserted. When PCMCIA interface is selected in area 5 or 6, in addition to

CS5/CS6, CE2A/CE2B

are asserted for the corresponding bytes accessed.

For virtual address spaces P0 and P3, when the memory management unit (MMU) is on, any

physical address can be generated by the MMU for a virtual address. Consequently, figure 10.2

can be applied when the MMU is off, and when the MMU is on and the physical addresses

corresponding to virtual addresses are identical except for the top 3 bits. When virtual addresses

are translated to arbitrary physical addresses, refer to table 10.3, Physical Address Space Map.

,,,,

,,,

,,,,

Area 0 (

CS0)

Area 1 (

CS1)

Area 2 (

CS2)

Area 3 (

CS3)

Area 4 (

CS4)

Area 5 (

CS5)

Area 6 (

CS6)

H'00000000

H'20000000

H'40000000

H'60000000

H'80000000

H'A0000000

H'C0000000

H'E0000000

H'00000000

H'04000000

H'08000000

H'0C000000

H'10000000

H'14000000

H'18000000

Reserved area

Physical address space

Virtual address space

P0, U0

Figure 10.2 Correspondence between Virtual Address Space and Physical Address Space

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