| 数据搜索系统,热门电子元器件搜索 |
|
SH7708 数据表(PDF) 210 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7708 数据表(HTML) 210 Page - Renesas Technology Corp |
|
210 / 633 page ![]() 192 10.1.4 Register Configuration The BSC has 11 registers (table 10.2). The synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, refreshes, and PCMCIA devices. Table 10.2 Register Configuration Name Abbr. R/W Initial Value* 2 Address Bus Width Bus control register 1 BCR1 R/W H'0000 H'FFFFFF60 16 Bus control register 2 BCR2 R/W H'3FFC H'FFFFFF62 16 Wait state control register 1 WCR1 R/W H'3FFF H'FFFFFF64 16 Wait state control register 2 WCR2 R/W H'FFFF H'FFFFFF66 16 Individual memory control register MCR R/W H'0000 H'FFFFFF68 16 DRAM control register DCR R/W H'0000 H'FFFFFF6A 16 PCMCIA control register PCR R/W H'0000 H'FFFFFF6C 16 Refresh timer control/status register RTCSR R/W H'0000 H'FFFFFF6E 16 Refresh timer counter RTCNT R/W H'0000 H'FFFFFF70 16 Refresh time constant register RTCOR R/W H'0000 H'FFFFFF72 16 Refresh count register RFCR R/W H'0000 H'FFFFFF74 16 SDRAM mode register, area 2 SDMR W — H'FFFFD000– H'FFFFDFFF 8 SDRAM mode register, area 3 H'FFFFE000– H'FFFFEFFF Notes: 1. For details see section 10.2.8, Synchronous DRAM Mode Register. 2. Initialized during a power-on reset. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |