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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 219 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 219 Page - Renesas Technology Corp |
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219 / 633 page  201 Bit 12: HIZCNT Description 0 RAS and CAS signals become high-impedance (High-Z) in standby mode and in bus-released state. (Initial value) 1 RAS and CAS signals drive in standby mode and in bus-released state. Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only. Bit 11: ENDIAN Description 0 (On reset) Endian setting external pin (MD5) is low. Indicates the SH7708 Series is set as big-endian. 1 (On reset) Endian setting external pin (MD5) is high. Indicates the SH7708 Series is set as little-endian. Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): These bits specify whether to use burst ROM in physical space area 0. When burst ROM is used, they set the number of burst transfers. Bit 10: A0BST1 Bit 9: A0BST0 Description 0 0 Access area 0 as normal memory. (Initial value) 1 Access area 0 as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 1 0 Access area 0 as burst ROM (8 consecutive accesses). Can be used only when bus width is 8 or 16. 1 Access area 0 as burst ROM (16 consecutive accesses). Can be used only when bus width is 8. Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): These bits specify whether to use burst ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode are used, they set the number of burst transfers. Bit 8: A5BST1 Bit 7: A5BST0 Description 0 0 Access area 5 as normal memory. (Initial value) 1 Burst access of area 5 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 1 0 Burst access of area 5 (8 consecutive accesses). Can be used only when bus width is 8 or 16. 1 Burst access of area 5 (16 consecutive accesses). Can be used only when bus width is 8. |
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