SH7708 datasheet(223/633 Pages) RENESAS

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205

Bit:

Bit name: WAITSEL*

—

A6IW1

A6IW0

A5IW1

A5IW0

A4IW1

A4IW0

Initial value:

0111111

R/W:

R/W

Bit:

6543210

Bit name:

A3IW1

A3IW0

A2IW1

A2IW0

A1IW1

A1IW0

A0IW1

A0IW0

Initial value:

1111111

R/W:

R/W

Note: * SH7708R A-mask version only

Bits 15 and 14 —Reserved: These bits always read 0. The write value should always be 0.

Bit 15—WAIT Signal Sampling Timing Specification (WAITSEL) [A-mask version only]

Bit 15: WAITSEL

Description

WAIT signal is sampled at rise of CKIO

In this case, the WAIT signal should be input synchronously

(Initial value)

WAIT signal is sampled at fall of CKIO

In this case, the WAIT signal can be input asynchronously

Bits 2n + 1, 2n—Area n (6–0) Intercycle Idle Specification (AnIW1, AnIW0): These bits specify

the number of idles inserted between bus cycles when switching between physical space area n (6–

0) to another space or between a read access to a write access in the same physical space.

Bit 2n + 1: AnIW1

Bit 2n: AnIW0

Description

No idle cycles

1 idle cycle inserted

2 idle cycles inserted

3 idle cycles inserted

(Initial value)

SH7708 数据表(PDF) 223 Page - Renesas Technology Corp

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