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SH7708 数据表(PDF) 227 Page - Renesas Technology Corp

部件名 SH7708
功能描述  SuperH??RISC engine
PDF  633 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SH7708 数据表(HTML) 227 Page - Renesas Technology Corp

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• For Normal Memory
Description
Bit 4: A1-2W0
Bit 3: A1-2W0
Inserted Wait States
WAIT Pin
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled (Initial value)
• For DRAM, Synchronous DRAM
Description
Bit 4: A1-2W0
Bit 3: A1-2W0
DRAM:
CAS Assert Period
SDRAM: CAS Latency
00
1
1
11
1
10
2
2
1
3
3
(Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): These bits specify the number of wait
states inserted in physical space area 0. They also specify the burst pitch for burst transfer.
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Bit 2:
A0W2
Bit 1:
A0W1
Bit 0:
A0W0
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer
WAIT Pin
0
0
0
0
Ignored
2
Enabled
1
1
Enabled
2
Enabled
1
0
2
Enabled
3
Enabled
1
3
Enabled
4
Enabled
1
0
0
4
Enabled
4
Enabled
1
6
Enabled
6
Enabled
1
0
8
Enabled
8
Enabled
1
10 (Initial value) Enabled
10
Enabled
10.2.5
Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies
RAS
and
CAS timing and burst control for DRAM (area 3 only), synchronous DRAM (areas 2 and 3),



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