SH7708 datasheet(229/633 Pages) RENESAS

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Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): These bits set the synchronous

DRAM write-precharge delay time. This designates the time between the end of a write cycle and

the next bank-active command. This is valid only when synchronous DRAM is connected. After

the write cycle, the next bank-active command is not issued for the period TPC + TRWL.

Bit 11: TRWL1

Bit 10: TRWL0

Description

1 cycle

(Initial value)

2 cycles

3 cycles

Reserved (cannot be set)

Bits 9 and 8—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When DRAM

interface is selected as connected memory, the TRAS bits set the

RAS assertion period for CAS-

before-

RAS refreshes. When pseudo-SRAM interface is selected, they set the OE/RFSH assertion

period for auto-refreshes. When synchronous DRAM interface is selected, no bank-active

command is issued during the period TPC + TRAS after an auto-refresh command.

In the SH7708, set the same values in the TRAS bits in MCR and DCR.

Bit 9: TRAS1

Bit 8: TRAS0

Description

2 cycles

(Initial value)

3 cycles

4 cycles

5 cycles

Bit 7—Reserved: This bit always reads 0. The write value should always be 0.

Bit 6—Burst Enable (BE): Specifies whether to conduct a burst access of DRAM or pseudo-

SRAM. When accessing synchronous DRAM, burst access is always carried out, regardless of this

bit’s designation.

Bit 6: BE

Description

Burst disabled

(Initial value)

With DRAM interface, high-speed page mode access

With pseudo-SRAM interface, continuous data transfer in static column

mode

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