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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 226 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 226 Page - Renesas Technology Corp |
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226 / 633 page  208 Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): These bits specify the number of wait states inserted in physical space area 3. External wait input is enabled only when normal memory is used, and is ignored when DRAM, synchronous DRAM, or pseudo-SRAM is used. • For Normal Memory Description Bit 6: A3W0 Bit 5: A3W0 Inserted Wait States WAIT Pin 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled (Initial value) • For DRAM, SDRAM, Pseudo-SRAM Description Bit 6: A3W1 Bit 5: A3N0 DRAM: CAS Assert Period SDRAM: CAS Latency PSRAM: OE, WE Assert Period 00 1 1 1 11 1 1 10 2 2 2 1 3 3 3 (Initial value) Bits 4 and 3—Areas 1 and 2 Wait Control (A1–2W1, A1–2W0): These bits specify the number of wait states inserted in physical space areas 1 and 2. External wait input is enabled only when normal memory is used, and is ignored when DRAM or synchronous DRAM is used. |
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