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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 230 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 230 Page - Renesas Technology Corp |
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230 / 633 page  212 Bit 5—Memory Data Size (SZ): Specifies the memory data bus size for DRAM, synchronous DRAM, and pseudo-SRAM. Always set this bit to 1 when synchronous DRAM is used. Takes precedence over the BCR2 register designation. Bit 5: SZ Description 0 Word (16-bit) (Initial value) 1 Longword (32-bit) Bits 4 and 3—Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for DRAM and synchronous DRAM. The actual address shift value differs between DRAM interface and synchronous DRAM interface. For DRAM Interface: Bit 4: AMX1 Bit 3: AMX0 Description 0 0 8-bit column address product (Initial value) 1 9-bit column address product 1 0 10-bit column address product 1 11-bit column address product For Synchronous DRAM Interface: Bit 4: AMX1 Bit 3: AMX0 Description 0 0 16-Mbit product (1M × 16 bits) (Initial value) 1 16-Mbit product (2M × 8 bits) 1 0 16-Mbit product (4M × 4 bits) 1 4-Mbit product (256k × 16 bits) Bit 2—Refresh Control (RFSH): Determines whether or not refreshing of DRAM, synchronous DRAM, and pseudo-SRAM is performed. The timer for generation of the refresh request frequency can also be used as an interval timer. Bit 2: RFSH Description 0 No refresh (Initial value) 1 Refresh |
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