SH7708 datasheet(247/633 Pages) RENESAS

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10.3.2

Description of Areas

Area 0: Area 0 physical address bits A28–A26 are 000. Address bits A31–A29 are ignored and

the address range is H'00000000 + H'20000000

× n – H'03FFFFFF + H'20000000 × n (n = 0–6, n

= 1–6 is the shadow space).

Normal memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte,

word, or longword can be selected as the bus width using external pins. MD3 and MD4 on a

power-on reset. For details, see Memory Size in section 10.1.5. When the Area 0 space is

accessed, the

CS0 signal is asserted. The RD signal that can be used as OE and the WE0–WE3

signals for write control are also asserted. The number of bus cycles is selected between 0 and 10

wait cycles using the A0W2–A0W0 bits in WCR2. Also, any number of waits can be inserted in

each bus cycle by means of the external wait pin (

WAIT). When the burst function is used, the bus

cycle pitch of the burst cycle is determined within a range of 2–10 according to the number of

waits.

Area 1: Area 1 physical address bits A28–A26 are 001. Address bits A31–A29 are ignored and

the address range is H'04000000 + H'20000000

× n – H'07FFFFFF + H'20000000 × n (n = 0–6, n

= 1–6 is the shadow space).

Only normal memories like SRAM and ROM can be connected to this space. Byte, word, or

longword can be selected as the bus width using the A1SZ1–A1SZ0 bits in BCR2. When the Area

1 space is accessed, the

CS1 signal is asserted. The RD signal that can be used as OE and the

WE0–WE3 signals for write control are also asserted. The number of bus cycles is selected

between 0 and 3 wait cycles using the A12W1–A12W0 bits in WCR2. Also, any number of waits

can be inserted in each bus cycle by means of the external wait pin (

WAIT).

Area 2: Area 2 physical address bits A28–A26 are 010. Address bits A31–A29 are ignored and

the address range is H'08000000 + H'20000000

× n – H'0BFFFFFF + H'20000000 × n (n = 0–6, n

= 1–6 is the shadow space).

Normal memories like SRAM and ROM, as well as DRAM and synchronous DRAM, can be

connected to this space. Byte, word, or longword can be selected as the bus width using the

A2SZ1–A2SZ0 bits in BCR2 for normal memory. For synchronous DRAM, set longword using

the SZ bit in MCR. When DRAM is connected to area 2, the bus width is fixed at 16 bits. The bus

width for area 3 also needs to be 16 bits.

When the area 2 space is accessed, the

CS2 signal is asserted. When normal memories are

connected, the

RD signal that can be used as OE and the WE0–WE3 signals for write control are

also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the

A12W1 to A12W0 bits in WCR2. When normal memory is connected, only, any number of waits

can be inserted in each bus cycle by means of the external wait pin (

WAIT).

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