SH7708 datasheet(250/633 Pages) RENESAS

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The number of bus cycles is selected between 0 and 10 wait cycles using the A6W2–A6W0 bits in

WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait

pin (

WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined

within a range of 2–10 according to the number of waits. The setup and hold times of

address/

CE1B/CE2B for the read/write strobe signals can be set within a range of 0.5–3.5 cycles

using A6TED1–A6TED0 and A6TEH1–A6TEH0.

If PCMCIA is used in area 6, synchronous DRAM is used at the same time, and a synchronous

DRAM auto-refresh (CAS-before-RAS refresh) request is issued simultaneously, area 6 card

enable signals

CS6 and CE2B may be asserted earlier than usual, at the same time as the

immediately preceding auto-refresh cycle. When both PCMCIA and synchronous DRAM are

used, they should be used in area 5. When area 5 is used, the system design should provide for CS

to be asserted early without causing any problems.

10.3.3

Basic Interface

Basic Timing: The basic interface of the SH7708 Series uses strobe signal output because mainly

SRAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A

no-wait normal access is completed in two cycles. The

BS signal is asserted for one cycle to

indicate the start of a bus cycle. The

CSn signal is negated on the T2 clock falling edge to secure

the negation period. Therefore, at minimum pitch, there is a half-cycle negation period.

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 32 bits are always

read in a 32-bit device, and 16 bits in a 16-bit device. When writing, only the

WE signal for the

byte to be written is asserted. For details, see section 10.3.1, Endian/Access Size and Data

Alignment.

Read/write for cache fill or copy-back follows the set bus width and transfers a total of 16 bytes

continuously. The bus is not released during this transfer. For cache misses that occur during byte

or word operand accesses or branching to odd word boundaries, the fill is always performed by

longword accesses on the chip-external interface. Write-through area write access and

noncacheable read/write access is based on the actual address size.

SH7708 数据表(PDF) 250 Page - Renesas Technology Corp

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