SH7708 datasheet(249/633 Pages) RENESAS

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Area 5: Area 5 physical address bits A28–A26 are 101. Address bits A31–A29 are ignored and

the address range is the 64 Mbytes at H'14000000 + H'20000000

× n – H'17FFFFFF +

H'20000000

× n (n = 0–6, n = 1–6 is the shadow space).

Normal memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be

connected to this space. PCMCIA interfaces only use their IC memory card interface, so the

address range becomes the 32 Mbytes at H'14000000 + H'20000000

× n – H'15FFFFFF +

H'20000000

× n (n = 0–6, n = 1–6 is the shadow space).

For normal memory and burst ROM, byte, word, or longword can be selected as the bus width

using the A5SZ1–A5SZ0 bits in BCR2. For the PCMCIA interface, byte, and word can be

selected as the bus width using the A5SZ1–A5SZ0 bits in BCR2.

When the area 5 space is accessed and normal memory is connected, the

CS5 signal is asserted.

The

RD signal that can be used as OE and the WE0–WE3 signals for write control are also

asserted. When the PCMCIA interface is used, the

CE1 signal, CE2 signal, OE signal, and WE

signal are asserted.

The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2–A5W0 bits in

WCR2. Also, any number of waits can be inserted in each bus cycle by means of the external wait

pin (

WAIT). When a burst function is used, the bus cycle pitch of the burst cycle is determined

within a range of 2–10 according to the number of waits. The setup and hold times of

address/

CE1A/CE2A for the read/write strobe signals can be set within a range of 0.5–3.5 cycles

using the A5TED1–A5TED0 and A5TEH1–A5TEH0 bits in the PCR register.

Area 6: Area 6 physical address bits A28–A26 are 110. Address bits A31–A29 are ignored and

the address range is the 64 Mbytes at H'18000000 + H'20000000

× n – H'1BFFFFFF +

H'20000000

× n (n = 0–6, n = 1–6 is the shadow space).

Normal memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be

connected to this space. When the PCMCIA interface is used, the IC memory card interface

address range is the 32 Mbytes at H'18000000 + H'20000000

× n – H'19FFFFFF + H'20000000 ×

n and the I/O card interface address range is the 32 Mbytes at H'1A000000 + H'20000000

× n –

H'1BFFFFFF + H'20000000

× n (n = 0–6, n = 1–6 is the shadow space).

For normal memory and burst ROM, byte, word, or longword can be selected as the bus width

using the A6SZ1–A6SZ0 bits in BCR2. For the PCMCIA interface, byte, and word can be

selected as the bus width using the A6SZ1–A6SZ0 bits in BCR2.

When the area 6 space is accessed and normal memory is connected, the

CS6 signal is asserted.

The

RD signal that can be used as OE and the WE0–WE3 signals for write control are also

asserted. When the PCMCIA interface is used, the

CE1B signal, CE2B signal, OE signal, and

WE1 , ICORD, and ICOWR signals are asserted.

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