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H8/3003 数据表(PDF) 548 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 548 Page - Renesas Technology Corp |
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548 / 715 page  Table 18-4 Bus Timing (cont) Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz 10 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit Write data delay time tWDD — 75— 75 — 60ns Write data setup time 1 tWDS1 60 — 65 — 35 — Write data setup time 2 tWDS2 15 — 10 — 5 — Write data hold time tWDH 25 — 20 — 20 — Read data access tACC1* — 110 — 100 — 55 time 1 Read data access tACC2* — 230 — 200 — 115 time 2 Read data access tACC3* —55 — 50 — 25 time 3 Read data access tACC4* — 160 — 150 — 85 time 4 Precharge time tPCH* 85 — 60 — 40 — Wait setup time tWTS 40 — 40 — 25 — ns Figure 18-6 Wait hold time tWTH 10 — 10 — 5 — Bus request setup ime tBRQS 40 — 40 — 40 — ns Figure 18-18 Bus acknowledge tBACD1 —60 — 50 — 30 delay time 1 Bus acknowledge tBACD2 —60 — 50 — 30 delay time 2 Bus-floating time tBZD — 70 — 70 — 40 Note is on next page. Test Conditions Figure 18-4, Figure 18-5 530 |
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