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H8/3003 数据表(PDF) 550 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 550 Page - Renesas Technology Corp |
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550 / 715 page  Table 18-5 Refresh Controller Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz 10 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit RAS delay time 1 tRAD1 — 60— 50 — 30ns RAS delay time 2 tRAD2 —60 — 50 — 30 RAS delay time 3 tRAD3 —60 — 50 — 30 Row address hold time* tRAH 25 — 20 — 15 — RAS precharge time* tRP 85 — 70 — 40 — CAS to RAS precharge tCRP 85 — 70 — 40 — time* CAS pulse width tCAS 110 — 85 — 40 — RAS access time* tRAC — 160 — 150 — 85 Address access time tAA — 105 — 75 — 55 CAS access time tCAC —50 — 50 — 25 Write data setup time 3 tWDS3 75 — 50 — 40 — CAS setup time* tCSR 20 — 15 — 15 — Read strobe delay time tRSD —60 — 50 — 30 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 38 (ns) tCAC = 1.0 × tcyc – 75 (ns) tRAC = 2.0 × tcyc – 90 (ns) tCSR = 0.5 × tcyc – 43 (ns) tRP = tCRP = 1.0 × tcyc – 40 (ns) At 10 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 30 (ns) tCAC = 1.0 × tcyc – 50 (ns) tRAC = 2.0 × tcyc – 50 (ns) tCSR = 0.5 × tcyc – 35 (ns) tRP = tCRP = 1.0 × tcyc – 30 (ns) At 16 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 16 (ns) tCAC = 1.0 × tcyc – 38 (ns) tRAC = 2.0 × tcyc – 40 (ns) tCSR = 0.5 × tcyc – 16 (ns) tRP = tCRP = 1.0 × tcyc – 23 (ns) Test Conditions Figure 18-7 to Figure 18-13 532 |
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