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H8/3003 数据表(PDF) 552 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 552 Page - Renesas Technology Corp |
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552 / 715 page  Table 18-7 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz 10 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit DMAC DREQ setup tDRQS 40 — 30 — 30 — ns Figure 18-27 time DREQ hold tDRQH 10 — 10 — 10 — time TEND delay tTED1 — 100 — 50 — 50 Figure 18-25, time 1 Figure 18-26 TEND delay tTED2 — 100 — 50 — 50 time 2 ITU Timer output tTOCD — 100 — 100 — 100 ns Figure 18-21 delay time Timer input tTICS 50 — 50 — 50 — setup time Timer clock tTCKS 50 — 50 — 50 — Figure 18-22 input setup time Single tTCKWH 1.5 — 1.5 — 1.5 — tCYC edge Both tTCKWL 2.5 — 2.5 — 2.5 — edges SCI Asyn- tSCYC 4 — 4 — 4 — Figure 18-23 chronous Syn- tSCYC 6— 6 — 6 — chronous Input clock rise tSCKR — 1.5 — 1.5 — 1.5 time Input clock fall tSCKR — 1.5 — 1.5 — 1.5 time Input clock tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tSCYC pulse width Test Conditions 534 Timer clock pulse width Input clock cycle |
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