H8SLASH3003 datasheet(102/715 Pages) RENESAS

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5.2.3 IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ7 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to

IRQ0 interrupt requests.

Bits 7 to 0

IRQ7F to IRQ0F

Description

[Clearing conditions]

(Initial value)

0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.

IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.

IRQnSC = 1 and IRQn interrupt exception handling is carried out.

[Setting conditions]

IRQnSC = 0 and IRQn input is low.

IRQnSC = 1 and IRQn input changes from high to low.

Note: n = 7 to 0

Bit

Initial value

Read/Write

IRQ7F

R/(W)

These bits indicate IRQ to IRQ interrupt request status

Note:

Only 0 can be written, to clear flags.

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

IRQ to IRQ flags

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