H8SLASH3003 datasheet(106/715 Pages) RENESAS

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Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF).

Figure 5-3 Timing of Setting of IRQnF

Interrupts IRQ0 to IRQ7 have vector numbers 12 to 19. These interrupts are detected regardless of

whether the corresponding pin is set for input or output. When using a pin for external interrupt

input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI

input or output.

5.3.2 Internal Interrupts

Thirty-four internal interrupts are requested from the on-chip supporting modules.

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Each on-chip supporting module has status flags for indicating interrupt status, and enable

bits for enabling or disabling interrupts.

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Interrupt priority levels can be assigned in IPRA and IPRB.

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ITU and SCI interrupt requests can activate the DMAC, in which case no interrupt request is

sent to the interrupt controller, and the I and UI bits are disregarded.

5.3.3 Interrupt Vector Table

Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the

default priority order, smaller vector numbers have higher priority. The priority of interrupts other

than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order

shown in table 5-3.

IRQn

IRQnF

input pin

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