H8SLASH3003 datasheet(203/715 Pages) RENESAS

203 / 715 page

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)

requested when the DTE bit is cleared to 0.

Bit 3

DTIE

Description

The DEND interrupt requested by DTE is disabled

(Initial value)

The DEND interrupt requested by DTE is enabled

Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer

activation source. Some of the selectable sources differ between channels A and B.

Channel A

Bit 2

Bit 1

Bit 0

DTS2A

DTS1A

DTS0A

Description

Compare match/input capture A interrupt from ITU

(Initial value)

channel 0

Compare match/input capture A interrupt from ITU channel 1

Compare match/input capture A interrupt from ITU channel 2

Compare match/input capture A interrupt from ITU channel 3

100Transmit-data-empty interrupt from SCI channel 0 or 1*2

Receive-data-full interrupt from SCI channel 0 or 1*2

1—*1

Transfer in full address mode

Notes: 1. See section 8.3.4, Data Transfer Control Register (DTCR).

2. DMAC channels 0 and 1 accept transmit-data-empty and receive-data-full interrupts

from SCI channel 0. DMAC channels 2 and 3 accept transmit-data-empty and receive-

data-full interrupts from SCI channel 1.

185

H8/3003 数据表(PDF) 203 Page - Renesas Technology Corp