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H8/3003 数据表(PDF) 204 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 204 Page - Renesas Technology Corp |
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204 / 715 page  Channel B Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Description 0 0 0 Compare match/input capture A interrupt from ITU (Initial value) channel 0 1 Compare match/input capture A interrupt from ITU channel 1 1 0 Compare match/input capture A interrupt from ITU channel 2 1 Compare match/input capture A interrupt from ITU channel 3 100Transmit-data-empty interrupt from SCI channel 0 or 1* 1 Receive-data-full interrupt from SCI channel 0 or 1* 1 0 Falling edge of DREQ input 1 Low level of DREQ input Note: * DMAC channels 0 and 1 accept transmit-data-empty and receive-data-full interrupts from SCI channel 0. DMAC channels 2 and 3 accept transmit-data-empty and receive-data-full interrupts from SCI channel 1. The same internal interrupt can be selected as an activation source for two or more channels at once. In that case the channels are activated in a priority order, highest-priority channel first. For the priority order, see section 8.4.9, Multiple-Channel Operation. When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a CPU interrupt. 186 |
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